Advanced Packaging / Chiplet

Intelligence Summary: Advanced Packaging / Chiplet

Node Identity: Advanced packaging and chiplet technology represent China's primary workaround for US export controls on advanced lithography. The chiplet approach involves designing complex integrated circuits as multiple smaller chip "lets" — each manufactured at a process node achievable with available lithography — and then combining them into a single package using advanced interconnect technologies (2.5D, 3D, silicon interposer, or fan-out packaging). At least 20 policy documents from local to central Chinese government levels have referred to chiplets as part of a broader semiconductor strategy.

Strategic Relevance: Advanced packaging and chiplet technology is strategically critical for the FRC weapons program because it provides the architectural workaround for the EUV lithography bottleneck. The MH370 Rosetta Stone established that FRC weaponization requires complex control system-on-chip (SoC) devices — chips that integrate processors, memory interfaces, analog-to-digital converters, and radiation-hardened logic on a single die. Producing such complex chips monolithically requires leading-edge (3-5nm) lithography, which is restricted by US export controls. The chiplet approach solves this by decomposing the complex SoC into multiple simpler chiplets — each manufacturable at 14nm or 28nm using available DUV lithography — and combining them in a single package with high-bandwidth interconnects. The result is a system with leading-edge complexity built from trailing-edge components. For FRC control systems, this approach is particularly suitable because the radiation-hardening requirements favor larger geometries (28nm+) for individual chiplets, while the overall system complexity is achieved through packaging.

Technical Focus / Capabilities:

• Multi-Chiplet Decomposition: Breaking complex FRC control SoCs into multiple simpler chiplets manufacturable at available process nodes
• 2.5D/3D Packaging: Silicon interposer and through-silicon-via (TSV) technologies for high-bandwidth inter-chiplet communication
• YMTC Xtacking Validation: YMTC's Xtacking 3D NAND architecture demonstrates a successful chiplet approach in production
• HiSilicon Design Expertise: HiSilicon's multi-die packaging experience provides the design capability for chiplet-based FRC control systems
• Policy Support: 20+ government policy documents support chiplet development as a strategic priority

Network Linkage: Advanced Packaging / Chiplet maintains 3 documented connections: enables Huawei (advanced packaging for telecommunications and defense chips); enables HiSilicon (multi-die SoC design for FRC control); accelerated by Chiplet Technology Workaround (the strategic framework). The chiplet approach is the architectural workaround that enables complex FRC control system fabrication without EUV lithography, directly supporting the Microelectronics Crash Program's objectives.