Chiplet Technology Workaround

Intelligence Summary: Chiplet Technology Workaround

Node Identity: The Chiplet Technology Workaround is a "Hardware" group node representing China's advanced packaging strategy to circumvent US export controls on leading-edge EUV lithography. By combining multiple smaller chiplets into a single high-performance package using 2.5D and 3D advanced packaging, China can build the complex control systems needed for FRC devices without access to ASML's EUV lithography tools. At least 20 policy documents from local to central government levels reference chiplets as part of a broader semiconductor strategy.

Strategic Relevance: Chiplets directly enable the Microelectronics Crash Program by providing a viable path to high-performance rad-hard control electronics despite lithography restrictions. The US October 2022 export controls restricted advanced lithography equipment and high-performance computing chips to China — but advanced packaging technology is less restricted, creating a critical loophole. China's approach: manufacture multiple function-specific chiplets at mature process nodes (which are not restricted), then integrate them via advanced packaging into a system-on-package with performance approaching monolithic advanced-node chips. This is particularly relevant for FRC control systems, which require heterogeneous integration of radiation-hardened logic, high-speed ADCs, and power management — functions that map naturally to a chiplet architecture.

Technical Focus / Capabilities:

• 2.5D/3D Advanced Packaging: Combining multiple chiplets with through-silicon vias (TSVs) and micro-bump interconnects into a single package
• Heterogeneous Integration: Separating rad-hard logic, analog front-end, and power management into specialized chiplets manufactured at different nodes
• YMTC Xtacking Architecture: Novel chiplet-style approach to 3D NAND where memory cells and controller logic are fabricated on separate wafers and bonded — demonstrating China's indigenous advanced packaging capability
• HiSilicon Design Capability: Huawei's chip design arm researches advanced packaging/chiplet approaches for domestic silicon

Network Linkage: The Chiplet Workaround maintains 3 documented connections: uses SMIC for chiplet fabrication; implements the Advanced Packaging / Chiplet concept. Necessitated by US Export Controls (2018) and October 2022 Export Controls. ASML Lithography Restrictions accelerated this approach. Enabled by the Microelectronics Crash Program. The Advanced Packaging concept enables Huawei and HiSilicon, creating a path from lithography workaround to defense-grade chip design.