Radiation Tolerant Electronics

Summary

This book is a printed edition of the Special Issue ‘Radiation Tolerant Electronics’ published in the journal Electronics, edited by Paul Leroux. It compiles cutting-edge research articles addressing the challenges of ionizing radiation and single-event effects in electronic components and integrated circuits. Topics covered include radiation-hardened design techniques for power MOSFETs, bipolar transistors, instrumentation amplifiers, RF transceivers, time-to-digital converters, voltage references, CMOS ring oscillators, frequency synthesizers, digital circuits, and SRAM-based FPGAs for space and high-energy physics applications.

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electronics Radiation Tolerant Electronics Edited by Paul Leroux Printed Edition of the Special Issue Published in Electronics www.mdpi.com/journal/electronics MDPI

Title Page

Radiation Tolerant Electronics

Imprint

Radiation Tolerant Electronics Special Issue Editor Paul Leroux MDPI • Basel • Beijing • Wuhan • Barcelona • Belgrade

Special Issue Editor Paul Leroux KU Leuven ESAT-ADVISE Belgium

Editorial Office MDPI St. Alban-Anlage 66 4052 Basel, Switzerland

This is a reprint of articles from the Special Issue published online in the open access journal Electronics (ISSN 2079-9292) from 2018 to 2019 (available at: https://www.mdpi.com/journal/electronics/special_issues/Radiation_Tolerant_Electronics)

For citation purposes, cite each article independently as indicated on the article page online and as indicated below: LastName, A.A.; LastName, B.B.; LastName, C.C. Article Title. Journal Name Year, Article Number, Page Range.

ISBN 978-3-03921-279-8 (Pbk) ISBN 978-3-03921-280-4 (PDF)

© 2019 by the authors. Articles in this book are Open Access and distributed under the Creative Commons Attribution (CC BY) license, which allows users to download, copy and build upon published articles, as long as the author and publisher are properly credited, which ensures maximum dissemination and a wider impact of our publications. The book as a whole is distributed by MDPI under the terms and conditions of the Creative Commons license CC BY-NC-ND.

Contents

Contents

About the Special Issue Editor … vii

Paul Leroux Radiation Tolerant Electronics Reprinted from: Electronics 2019, 8, 730, doi:10.3390/electronics8070730 … 1

Teng Wang, Xin Wan, Hu Jin, Hao Li, Yabin Sun, Renrong Liang, Jun Xu and Lirong Zheng Optimization of the Cell Structure for Radiation-Hardened Power MOSFETs Reprinted from: Electronics 2019, 8, 598, doi:10.3390/electronics8060598 … 4

Mohan Liu, Wu Lu, Xin Yu, Xin Wang, Xiaolong Li, Shuai Yao and Qi Guo Mechanism of Degradation Rate on the Irradiated Double-Polysilicon Self-Aligned Bipolar Transistor Reprinted from: Electronics 2019, 8, 657, doi:10.3390/electronics8060657 … 15

Kyungsoo Jeong, Duckhoon Ro, Gwanho Lee, Myounggon Kang and Hyung-Min Lee A Radiation-Hardened Instrumentation Amplifier for Sensor Readout Integrated Circuits in Nuclear Fusion Applications Reprinted from: Electronics 2018, 7, 429, doi:10.3390/electronics7120429 … 23

Jan Budroweit, Mattis Paul Jaksch Maciej Sznajder Proton Induced Single Event Effect Characterization on a Highly Integrated RF-Transceiver Reprinted from: Electronics 2019, 8, 519, doi:10.3390/electronics8050519 … 33

Bjorn Van Bockel, Jeffrey Prinzie and Paul Leroux Radiation Assessment of a 15.6 ps Single-Shot Time-to-Digital Converter in Terms of TID Reprinted from: Electronics 2019, 8, 558, doi:10.3390/electronics8050558 … 53

Charalambos M. Andreou, Diego M. González-Castaño, Simone Gerardin, Marta Bagatin, Faustino Gómez, Alessandro Paccagnella, Alexander V. Prokofiev, Arto Javanainen, Ari Virtanen, Valentino Liberali, Cristiano Calligaro, Daniel Nahmad and Julius Georgiou Low-Power, Subthreshold Reference Circuits for the Space Environment: Evaluated with γ-rays, X-rays, Protons and Heavy Ions Reprinted from: Electronics 2019, 8, 562, doi:10.3390/electronics8050562 … 64

Jeffrey Prinzie and Valentijn De Smedt Single Event Transients in CMOS Ring Oscillators Reprinted from: Electronics 2019, 8, 618, doi:10.3390/electronics8060618 … 88

V. Díez-Acereda, Sunil L. Khemchandani, J. del Pino and S. Mateos-Angulo RHBD Techniques to Mitigate SEU and SET in CMOS Frequency Synthesizers Reprinted from: Electronics 2019, 8, 690, doi:10.3390/electronics8060690 … 100

Maria Munoz-Quijada, Samuel Sanchez-Barea, Daniel Vela-Calderon, Hipolito Guzman-Miranda Fine-Grain Circuit Hardening Through VHDL Datatype Substitution Reprinted from: Electronics 2019, 8, 24, doi:10.3390/electronics8010024 … 114

Jeffrey Prinzie, Karel Appels, Szymon Kulis Optimal Physical Implementation of Radiation Tolerant High-Speed Digital Integrated Circuits in Deep-Submicron Technologies Reprinted from: Electronics 2019, 8, 432, doi:10.3390/electronics8040432 … 132

Chang Cai, Xue Fan, Jie Liu, Dongqing Li, Tianqi Liu, Lingyun Ke, Peixiong Zhao and Ze He Heavy-Ion Induced Single Event Upsets in Advanced 65 nm Radiation Hardened FPGAs Reprinted from: Electronics 2019, 8, 323, doi:10.3390/electronics8030323 … 142

Solomon Banteywalu, Baseem Khan, Valentijn De Smedt and Paul Leroux A Novel Modular Radiation Hardening Approach Applied to a Synchronous Buck Converter Reprinted from: Electronics 2019, 8, 513, doi:10.3390/electronics8050513 … 155

Leonardo Maria Reyneri, Alejandro Serrano-Cases, Yolanda Morilla, Sergio Cuenca-Asensi, Antonio Martínez-Álvarez A Compact Model to Evaluate the Effects of High Level C++ Code Hardening in Radiation Environments Reprinted from: Electronics 2019, 8, 653, doi:10.3390/electronics8060653 … 166

Honorio Martin, Pedro Martin-Holgado, Yolanda Morilla, Luis Entrena and Enrique San Millan Total Ionizing Dose Effects on a Delay-Based Physical Unclonable Function Implemented in FPGAs Reprinted from: Electronics 2018, 7, 163, doi:10.3390/electronics7090163 … 179

Luis Alberto Aranda, Pedro Reviriego and Juan Antonio Maestro Protecting Image Processing Pipelines against Configuration Memory Errors in SRAM-Based FPGAs Reprinted from: Electronics 2018, 7, 322, doi:10.3390/electronics7110322 … 190

About the Special Issue Editor

About the Special Issue Editor

Paul Leroux is Professor in the Department of Electrical Engineering (ESAT) of KU Leuven (University of Leuven), Belgium. He received M.Sc. and Ph.D. degrees in electronic engineering from KU Leuven in 1999 and 2004, respectively. From November 2011 to July 2016, he headed the Electrical Engineering Technology Cluster. Since August 2016 he had been the Campus Chair of KU Leuven, Geel Campus. His current research activities within the ESAT-ADVISE research group focus on radiation-hardened analog, mixed-signal, and RF IC design for communication and instrumentation in space, high-energy physics, and nuclear energy applications. His group is part of the CERN CMS collaboration, where Prof. Leroux is the KU Leuven team leader. Prof. Leroux has (co-)authored over 200 papers in international journals and conference proceedings. In 2010, he received the SCK-CEN Prof. Roger Van Geen Award from the FWO/FNRS for his highly innovative work on IC design for harsh radiation environments.

Editorial: Radiation Tolerant Electronics

electronics Editorial Radiation Tolerant Electronics Paul Leroux KU Leuven, Dept. Electrical Engineering (ESAT) - ADVISE, 2440 Geel, Belgium; [email protected] Received: 20 June 2019; Accepted: 25 June 2019; Published: 27 June 2019

1. Introduction Research on radiation tolerant electronics has increased rapidly over the last few years, resulting in many interesting approaches to model radiation effects and design radiation hardened integrated circuits and embedded systems. This research is strongly driven by the growing need for radiation hardened electronics for space applications, high-energy physics experiments such as those on the large hadron collider at CERN, and many terrestrial nuclear applications including nuclear energy and safety management. With the progressive scaling of integrated circuit technologies and the growing complexity of electronic systems, their ionizing radiation susceptibility has raised many exciting challenges, which are expected to drive research in the coming decade. Even though total ionizing dose effects in bulk CMOS are well known, little is still known on the radiation performance of advanced (FD-)SOI and FinFET technologies. Regarding single-event effects, the continued scaling has drastically increased the number of multiple-transistor or multiple-cell upsets, which requires not only new solutions to reduce the error rate in digital and mixed-signal ASICs, but also for FPGAs. The radiation hardness assurance of complex systems with multiple components in mixed technologies also necessitates new testing paradigms and verification methodologies to limit the time and cost for evaluation.

2. The Present Issue This Special Issue features fifteen articles highlighting recent breakthroughs in modeling radiation effects for the design of radiation hardened integrated circuits, radiation hardening in embedded systems, and radiation hardening assurance. The contents of these papers are introduced here. Two papers discuss the effect of radiation on advanced semiconductor devices such as dedicated power MOSFETs and double-polysilicon self-aligned bipolar transistors. In [1], the effects of cell structure adjustment on the performance of a power MOSFET were examined by first analyzing the design parameters. Next, a SEE- and TID-hardened power MOSFET was designed and fabricated. Results of the investigation confirmed the achievement of excellent radiation hardness and decent specific on-resistance for the device. Article [2] discussed the mechanism of degradation on the Irradiated Double-Polysilicon Self-Aligned Bipolar Transistor with a dose rate of 50 rad (Si)/s and 0.05 rad (Si)/s. The comparison of the high and low dose rate showed that the increase of the base current caused by low dose rate irradiation was larger than that caused by high dose rate irradiation, resulting in greater current gain degradation than that caused by the high dose rate, highlighting that the ELDRS effect may occur. Several papers discuss the total-dose and/or single-event radiation effects on custom designed analog, mixed signal, and RF integrated circuits. A radiation-hardened instrumentation amplifier for sensor readout integrated circuits was presented in [3] to target nuclear fusion applications. The circuit boasts TID effect monitoring and adaptive reference control functions. The radiation tolerance was verified through SPICE simulations with radiation-aware transistor models. In [4], the authors presented the proton induced SEE characterization of a highly integrated RF transceiver in 65 nm CMOS. The exposed proton energies were split into two test campaigns to induce high energy protons (up to 184 MeV) and low energy protons down to 4 MeV. The results showed a very low sensitivity to proton irradiation, independent of the proton energy. The total ionizing dose radiation assessment of a 15.6 ps single-shot Time-to-Digital Converter was presented in [5]. Two samples were irradiated and were able to reach a dose of 2.2 MGy before failing to meet specification due to an increased non-linearity error, originating from the increased mismatch in the charge-pump of the sampling circuit. A comprehensive evaluation of two subthreshold voltage reference circuits with respect to their resilience to SEE, TID, and TID/DD was performed in [6]. The evaluation was supported by measured results with γ-rays, x-rays, protons, and heavy ions. The high total doses applied in this range of experiments provide a complete evaluation of subthreshold circuits in the whole range of space applications, radiation physics instruments, and medical applications. The authors in [7] discussed a time-variant on Single-Event Transients (SETs) in integrated CMOS ring oscillators. The Impulse Sensitive Function (ISF) of the oscillator was used to analyze the impact of the relative moment when a particle hit the circuit. The analysis was based on simulations and verified experimentally with a Two-Photon Absorption (TPA) laser setup. Article [8] presented a comprehensive study of the effects of SETs and SEUs on a frequency synthesizer for the IEEE 802.15.4 standard. The blocks that work at low frequencies were not affected by ion impacts. However, high frequency circuits such as the VCO were more vulnerable. The VCO’s radiation tolerance was improved by using RC-filtering and a capacitive divider was introduced to improve the degraded phase noise. Two articles focus on the radiation hardening of digital circuits. A new approach to implement fine-grain circuit hardening was developed and validated in [9]. This offers a dedicated VHDL package as a new tool for mitigating soft errors on digital circuits, with minimal code modifications as the designer only has to select which signals or ports should be hardened and then change their datatype accordingly. Article [10] presented a novel method for the physical implementation of Triple Modular Redundant high-speed digital circuits. The method uses a distributed constraining approach for TMR branches to avoid long interconnects between voters. The method was tested with increasingly complex digital modules and showed results that improved as the design size increased. Three papers of this Special Issue target embedded radiation hardening in FPGA or microcontroller systems. In [11] single-event radiation hardening techniques for SRAM-based FPGAs in 65 nm CMOS technology were discussed. Both layout hardening techniques and configuration hardening techniques including ECC and TMR were employed for this FPGA. The heavy-ion results indicated a satisfactory radiation tolerance, especially for the DICE CRAMs. A novel four module radiation hardening approach for FPGA was presented in [12]. This was implemented on a zynq-7000 development board (Zybo) and it was shown that the proposed method could be used for a radiation tolerant synchronous buck converter design for applications requiring a relatively longer mission time, compared to the TMR and FMR techniques. In [13], a compact model was presented to evaluate the effects of high-level C++ code radiation hardening. The use of appropriate C++ classes facilitated the use of TMR. Additionally, the availability of an easy-to-use performance estimation model could be used for quick and effective radiation tolerance optimization of microcontroller systems. Finally, two articles presented a link between the research fields of cryptography and image processing, respectively. In [14] the authors presented the total ionizing dose effects on a delay-based physical unclonable function implemented in FPGAs for authentication and key generation in space systems. Article [15] discussed a novel method to protect series and parallel line-buffer-based image processing pipelines against configuration memory errors in SRAM-Based FPGAs. The proposed technique presented lower FPGA resource usage, and fewer false positive detections than the other techniques; moreover, the image processing system did not have to be stopped and rebooted upon errors due to the partial reconfiguration.

3. Future The wide range of articles in this Special Issue exemplifies the broadness of the field of radiation hardened micro-electronics. The dream to enable high performance computing, signal processing, and communication in the harshest and most diverse radiation environments presents the community with many research challenges. It inevitably brings researchers together from several disciplines ranging from nuclear and solid-state physics over advanced modeling approaches and creative circuit design techniques to the application of progressive algorithms and deep learning to optimize system performance for the most diverse applications under the harshest of conditions.

Acknowledgments: I would like to thank all of the researchers who submitted articles to this Special Issue for their excellent contributions. I am also grateful to all of the reviewers who helped in the evaluation of the manuscripts and made very valuable suggestions to improve the quality of the contributions. I would like to acknowledge the editorial board of MDPI Electronics, who invited me to guest edit this Special Issue. I am also grateful to the Electronics Editorial office staff who worked thoroughly to maintain the rigorous peer-review schedule and timely publication.

References

1. Wang, T.; Wan, X.; Jin, H.; Li, H.; Sun, Y.; Liang, R.; Xu, J.; Zheng, L. Optimization of the Cell Structure for Radiation-Hardened Power MOSFETs. Electronics 2019, 8, 598. [CrossRef]
2. Liu, M.; Lu, W.; Yu, X.; Wang, X.; Li, X.; Yao, S.; Guo, Q. Mechanism of Degradation Rate on the Irradiated Double-Polysilicon Self-Aligned Bipolar Transistor. Electronics 2019, 8, 657. [CrossRef]
3. Jeong, K.; Ro, D.; Lee, G.; Kang, M.; Lee, H.-M. A Radiation-Hardened Instrumentation Amplifier for Sensor Readout Integrated Circuits in Nuclear Fusion Applications. Electronics 2018, 7, 429. [CrossRef]
4. Budroweit, J.; Jaksch, M.P.; Sznajder, M. Proton Induced Single Event Effect Characterization on a Highly Integrated RF-Transceiver. Electronics 2019, 8, 519. [CrossRef]
5. Van Bockel, B.; Prinzie, J.; Leroux, P. Radiation Assessment of a 15.6ps Single-Shot Time-to-Digital Converter in Terms of TID. Electronics 2019, 8, 558. [CrossRef]
6. Andreou, C.M.; González-Castaño, D.M.; Gerardin, S.; Bagatin, M.; Gómez Rodriguez, F.; Paccagnella, A.; Prokofiev, A.V.; Javanainen, A.; Virtanen, A.; Liberali, V.; et al. Low-Power, Subthreshold Reference Circuits for the Space Environment: Evaluated with γ-rays, X-rays, Protons and Heavy Ions. Electronics 2019, 8, 562. [CrossRef]
7. Prinzie, J.; Smedt, V.D. Single Event Transients in CMOS Ring Oscillators. Electronics 2019, 8, 618. [CrossRef]
8. Díez-Acereda, V.L.; Khemchandani, S.; del Pino, J.; Mateos-Angulo, S. RHBD Techniques to Mitigate SEU and SET in CMOS Frequency Synthesizers. Electronics 2019, 8, 690.
9. Muñoz-Quijada, M.; Sanchez-Barea, S.; Vela-Calderon, D.; Guzman-Miranda, H. Fine-Grain Circuit Hardening Through VHDL Datatype Substitution. Electronics 2019, 8, 24. [CrossRef]
10. Prinzie, J.; Appels, K.; Kulis, S. Optimal Physical Implementation of Radiation Tolerant High-Speed Digital Integrated Circuits in Deep-Submicron Technologies. Electronics 2019, 8, 432. [CrossRef]
11. Cai, C.; Fan, X.; Liu, J.; Li, D.; Liu, T.; Ke, L.; Zhao, P.; He, Z. Heavy-Ion Induced Single Event Upsets in Advanced 65 nm Radiation Hardened FPGAs. Electronics 2019, 8, 323. [CrossRef]
12. Banteywalu, S.; Khan, B.; De Smedt, V.; Leroux, P. A Novel Modular Radiation Hardening Approach Applied to a Synchronous Buck Converter. Electronics 2019, 8, 513. [CrossRef]
13. Reyneri, L.M.M.; Serrano-Cases, A.; Morilla, Y.; Cuenca-Asensi, S.; Martínez-Álvarez, A. A Compact Model to Evaluate the Effects of High Level C++ Code Hardening in Radiation Environments. Electronics 2019, 8, 653. [CrossRef]
14. Martin, H.; Martin-Holgado, P.; Morilla, Y.; Entrena, L.; San-Millan, E. Total Ionizing Dose Effects on a Delay-Based Physical Unclonable Function Implemented in FPGAs. Electronics 2018, 7, 163. [CrossRef]
15. Aranda, L.A.; Reviriego, P.; Maestro, J.A. Protecting Image Processing Pipelines against Configuration Memory Errors in SRAM-Based FPGAs. Electronics 2018, 7, 322. [CrossRef]

Article: Optimization of the Cell Structure for Radiation-Hardened Power MOSFETs

electronics Article Optimization of the Cell Structure for Radiation-Hardened Power MOSFETs Teng Wang 1, Xin Wan 2,3,*, Hu Jin 2, Hao Li 2, Yabin Sun 4, Renrong Liang 5, Jun Xu 3,5 and Lirong Zheng 1 1 School of Information Science and Technology, Fudan University, Shanghai 200433, China 2 Aurorachip Co. Ltd., Zhejiang 314000, China 3 Center for High Reliability Power Semiconductor, Yangtze Delta Region Institute of Tsinghua University, Zhejiang 314000, China 4 School of Information Science Technology, East China Normal University, Shanghai 200241, China 5 Institute of Microelectronics, Tsinghua University, Beijing 100084, China

• Correspondence: [email protected]; Tel.: +86-151-2000-1156 Received: 16 March 2019; Accepted: 25 May 2019; Published: 28 May 2019

Abstract: Power MOSFETs specially designed for space power systems are expected to simultaneously meet the requirements of electrical performance and radiation hardness. Radiation-hardened (rad-hard) power MOSFET design can be achieved via cell structure optimization. This paper conducts an investigation of the cell geometrical parameters with major impacts on radiation hardness, and a rad-hard power MOSFET is designed and fabricated. The experimental results validate the devices’ total ionizing dose (TID) and single event effects (SEE) hardness to suitably satisfy most space power system requirements while maintaining acceptable electrical performance.

Keywords: radiation-hardened; single event gate rupture (SEGR); SEB; power MOSFETs

1. Introduction Power MOSFETs are widely applied in space power systems [1]. However, they are vulnerable to particle from galactic cosmic rays, solar flares, and radiation belts, which may cause total ionizing dose effects, single event gate rupture (SEGR) effects and single event burnout (SEB) effects [2,3]. There has been a substantial research on such radiation effects [4–7], whereas radiation hardening on power MOSFETs, the more necessary resolve, has only been discussed in a few articles [8–12] whose content mostly focused on a single hardening issue, such as SEB, SEGR, and TID. Apparently, these radiation effects, along with electrical performance, are essential considerations during the design and fabrication stage of a power MOSFET; moreover, many trade-offs should be decided when balancing between several electrical parameters and radiation survivability. This paper entails a description of the design and fabrication of TID-, SEB-, and SEGR-hardened power MOSFETs, on the basis of a careful optimization of the devices’ cell structure and doping profile. Experimental verifications conducted show excellent radiation hardness and acceptable electrical performance of such devices for space power systems.

2. Design Considerations 2.1. Cell Structure A power MOSFET chip is composed of several regions, including cell region, termination structure, gate bus, and gate pad. Of these, the cell region determines many electrical parameters and typically accounts for the majority of the chip area. However, it is also the most vulnerable region to irradiation. Normally, SEGR, SEB, and TID effects should be simultaneously mitigated in the cell region, whereas in other regions, only one of these effects is considered.

2.2. Oxide Thickness Gate oxide thickness is affected by three major factors, namely threshold voltage, SEGR effects and TID effects, and secondary factors as device capacitance and electro-static discharge (ESD) robustness. TID effects are mitigated by keeping the gate oxide as thin as possible [15]. Conversely, a thin gate oxide exhibits a reduced ability to withstand the SEGR effects [16]. Most power MOSFETs are designed within a pre-irradiation threshold voltage (Vth) of 2–4 V. Certain radiation hardness requires Vth to remain within such specifications after receiving a specified dose, followed by high-temperature annealing. On this basis, the chosen Vth is greatly influenced by the shifting behaviors. The shifts could be negative or positive, depending on the dominant type of radiation-induced charge [15]. For negative-shifting-dominated cases, a higher Vth can save additional room for Vth shifting and is thus preferred. By contrast, for positive-shifting-dominated cases, a lower Vth is preferred for the same reason. Once the gate oxide tOX is given, Vth can be adjusted by changing the doping density in the channel region. Likewise, SEGR effects are mitigated by keeping the tOX large enough to avoid dielectric breakdown. During a heavy ion strike, the dielectric strength is temporarily reduced. Models with more physical insight were proposed by Javanainen et al. [17], although a simple empirical expression with little physical justification is adopted in this work, as follows [16]: ECRIT = VGS / tOX = EBD / (1 + Z/44), (1) where ECRIT is the critical electric field of gate oxide that must withstand heavy-ion injection; EBD is the intrinsic dielectric breakdown strength of gate oxide, which is 10^7 V/cm for most thermal oxides; and Z is the atomic number of the injected heavy ions. In rad-hard power MOSFETs’ datasheets, SEE resistance ability is illustrated as a safe operating area under certain heavy-ion injection (SEE SOA) [18,19]. In principle, SEE SOA is expressed as a series of gate and drain voltage bias conditions. The negative gate bias is directly applied to the gate to contribute all its value to the gate dielectrics, whereas only a portion of the drain bias is coupled to the gate dielectrics after heavy-ion injection [20]. Therefore, the minimum gate oxide bounded by SEGR effects can be calculated as follows: tOX,min = (αVDS − VGS)(1 + Z/44) / EBD, (2) where α is the coupled ratio of drain voltage related to the device design, as discussed later. Note that the bias conditions considered here are the worst bias conditions for SEGR production and are, hence, used for SEGR testing. The shift in the threshold voltage due to TID effects is a major problem for all metal-oxide-semiconductor (MOS) devices. For power MOSFETs, the relatively thick gate oxide makes this issue more severe. The Vth shift has been attributed to two kinds of radiation-induced charges, namely oxide charges and interface traps [15]. Therefore, the Vth shift (ΔVth) is the sum of the oxide-charge-induced negative shift, named ΔVot, and the interface-trap-induced positive shift, named ΔVit. Both ΔVot and ΔVit are strongly related to tOX. The relationship can be expressed as follows [21]: ΔVot,it = (1/COX) * (-1/tOX) * integral_0^tOX (ρot,it(x)xdx), (3) where ρot,it is the charge distribution of radiation-induced oxide-trapped or interface-trapped charge. Reduction of tOX entails a two-fold effect. First, reducing tOX can reduce the Vth shift for a given charge density, which is attributed to a larger COX resulting from a thinner tox. Second, it can reduce charge generation for a given dose, as shown in Equation (3). The integration term can be simplified by introducing a uniform charge generation for the oxide charge, resulting in the expression [22]: ΔVot = -ΔQot / COX = -q g0 D tOX Yh σh / COX = -q g0 D Yh σh / εOX * tOX^2, (4) where q is the electric charge (expressed in Coulomb), g0 is the electron-hole pair generation rate in SiO2 (in pairs/cm3/rad(SiO2)), D is the total dose level in units of rad(SiO2), Yh is charge yield of holes, σh is trapping cross section for holes captured by hole traps in oxide, and εOX is the dielectric constant of SiO2. Interface traps generation is much more complicated. However, protons are considered to play a key role in the formation of interface traps. Moreover, the process of proton generation in the oxide is intimately related to the transport of holes. By introducing the parameter Yp, which is the product of ND’H (concentration of hydrogen-containing defects) and σD’H (cross section for proton release from these defects) [23], ΔVit can be expressed as: ΔVit = ΔQit / COX = q g0 D tOX Yh Yp σp / COX = q g0 D Yh Yp σp / εOX * tOX^2, (5) Combining Equations (4) and (5) allows the maximum tOX bounded by the TID effects to be expressed as follows: tOX,max = sqrt( (ΔVth,max * εOX) / (q g0 D Yh |Yp σp - σh|) ), (6) where ΔVth,max is the maximum allowed threshold shift.

2.3. JFET Region Width Parameter α has been introduced in Section 2.2 to account for the coupling of drain voltage to the gate dielectric. Based on Equation (2), the lower bound of tOX can be reduced with reduced α, which means that a larger range of tOX is available at the design stage. Moreover, α has been demonstrated to correlate with JFET region width (LJFET) and thus can be reduced, with a reduced LJFET [10]. The specific resistance contributed by the JFET region (RJFET,SP) can be expressed as: RJFET,SP = ρJFET * HJP * (LCELL / LJFET), (7) where ρJFET is the resistivity of the JFET region; HJP is body junction depth; LCELL is the cell pitch; and LJFET is the JFET region width.

2.4. P Body and P+ Well Doping In general, larger P-body depth (HJP) and higher doping concentrations (NBODY), as well as a reduced length between N+ source edge and P+ well edge (LBODY), are desirable for an SEB-hardened cell design.

3. Results Table 1. Key geometrical parameters and doping concentrations for device design:

• tox: 80 nm
• HJP: 3 μm
• LCELL: 10 μm
• LBODY: ~2 μm
• LJFET: ~3 μm
• NBODY: ~5 × 10^16 cm^-3 Chip area was 12 mm2, active area was 8.5 mm2. Median BVds around 120 V, median Ron around 44 mΩ, specific resistance 3.74 mΩ·cm2. Vth values fell in range 2.36–2.62 V. TID testing up to 150 krad(Si) followed by annealing at 100 °C for 168 h showed Vth shifts less than 0.25 V. Xe ion tests at LET = 66 MeV·cm2/mg showed no SEB or SEGR up to VDS = 100 V at VGS = 0 V.

Article: Mechanism of Degradation Rate on the Irradiated DPSA Bipolar Transistor

electronics Article Mechanism of Degradation Rate on the Irradiated Double-Polysilicon Self-Aligned Bipolar Transistor Mohan Liu, Wu Lu, Xin Yu, Xin Wang, Xiaolong Li, Shuai Yao and Qi Guo

Abstract: The latent enhanced low dose rate sensitivity (ELDRS) effect is observed in the double-polysilicon self-aligned (DPSA) technology PNP bipolar junction transistor (BJT) irradiated with high and low dose rate gamma rays. The three-stage degradation rate of the excess base current (ΔIB) is analyzed: (1) positive oxide trap charge accumulation dominating at high dose rate, vs. initial hole transport and interface state formation at low dose rate; (2) saturation/equilibrium between trap filling and recombination; and (3) hydrogen molecule cracking and deep defect interaction releasing protons and increasing interface traps under long exposure.

Article: A Radiation-Hardened Instrumentation Amplifier for Sensor Readout ICs in Nuclear Fusion Applications

electronics Article A Radiation-Hardened Instrumentation Amplifier for Sensor Readout Integrated Circuits in Nuclear Fusion Applications Kyungsoo Jeong, Duckhoon Ro, Gwanho Lee, Myounggon Kang and Hyung-Min Lee

Abstract: A nuclear fusion reactor requires a radiation-hardened sensor readout IC tolerant up to MGy levels. A three-op-amp fully differential instrumentation amplifier (IA) is proposed employing TID effect monitoring and adaptive reference control in 65 nm standard CMOS. It achieves adjustable gain between 3 and 15, bandwidth up to 400 kHz, 34.6 μW power consumption, and maintains stable operation over TID effects up to 1 MGy.

Article: Proton Induced Single Event Effect Characterization on a Highly Integrated RF-Transceiver

electronics Article Proton Induced Single Event Effect Characterization on a Highly Integrated RF-Transceiver Jan Budroweit, Mattis Paul Jaksch and Maciej Sznajder

Abstract: The Analog Devices AD9361 agile RF transceiver (65 nm SOI CMOS) was characterized under proton irradiation from 4 MeV to 184 MeV up to a total fluence of 1.00 × 10^11 p/cm2. The DUT exhibited no destructive single event latchup (SEL), very low SEU/MBU rates, and rare single event failure interrupts (SEFIs), making it a viable candidate for software-defined radio in space applications.

Article: Radiation Assessment of a 15.6 ps Single-Shot Time-to-Digital Converter in Terms of TID

electronics Article Radiation Assessment of a 15.6 ps Single-Shot Time-to-Digital Converter in Terms of TID Bjorn Van Bockel, Jeffrey Prinzie and Paul Leroux

Abstract: A 15.6 ps resolution single-shot time-to-digital converter (TDC) based on a multipath pseudo-differential ring oscillator inside a PLL was fabricated in 65 nm CMOS. Two samples demonstrated radiation tolerance up to 2.2 MGy (SiO2) while maintaining 15.6 ps resolution with DNL of 0.22 LSB rms and INL of 0.34 LSB rms.

Article: Low-Power, Subthreshold Reference Circuits for the Space Environment

electronics Article Low-Power, Subthreshold Reference Circuits for the Space Environment: Evaluated with γ-rays, X-rays, Protons and Heavy Ions Charalambos M. Andreou, Diego Miguel González-Castaño, Simone Gerardin, Marta Bagatin, Faustino Gómez Rodriguez, Alessandro Paccagnella, Alexander V. Prokofiev, Arto Javanainen, Ari Virtanen, Valentino Liberali, Cristiano Calligaro, Daniel Nahmad and Julius Georgiou

Abstract: Two subthreshold CMOS voltage reference circuits fabricated in 0.18 μm standard CMOS were evaluated under gamma rays, X-rays (up to 80 Mrad(Si)), protons, and heavy ions (Si, Kr, Xe). The circuits demonstrated robust operation, low temperature coefficients (12.9 to 15 ppm/°C), sub-4 μW power consumption, and no destructive latchup.

Article: Single Event Transients in CMOS Ring Oscillators

electronics Article Single Event Transients in CMOS Ring Oscillators Jeffrey Prinzie and Valentijn De Smedt

Abstract: A time-variant analysis using the Impulse Sensitive Function (ISF) was conducted to model and measure SETs in integrated 65 nm CMOS ring oscillators. Two-Photon Absorption laser experiments confirmed that phase errors strongly depend on the exact arrival time of charge injection relative to oscillator transition edges.

Article: RHBD Techniques to Mitigate SEU and SET in CMOS Frequency Synthesizers

electronics Article RHBD Techniques to Mitigate SEU and SET in CMOS Frequency Synthesizers V. Díez-Acereda, Sunil L. Khemchandani, J. del Pino and S. Mateos-Angulo

Abstract: Radiation effects on an IEEE 802.15.4 frequency synthesizer in 0.18 μm CMOS were analyzed. RHBD techniques including RC filtering of bias lines, capacitive dividers in the LC-VCO, and DICE/Gated Feedback Cells in dividers reduced VCO phase displacement by ~50%, shortened recovery time by 81%, and fully mitigated SEUs in dividers.

Article: Fine-Grain Circuit Hardening Through VHDL Datatype Substitution

electronics Article Fine-Grain Circuit Hardening Through VHDL Datatype Substitution Maria Muñoz-Quijada, Samuel Sanchez-Barea, Daniel Vela-Calderon and Hipolito Guzman-Miranda

Abstract: A VHDL package (‘triple_logic’) allows selective, fine-grain TMR circuit hardening simply by substituting standard signal types (std_logic, unsigned, etc.) with triple types (triple_logic, triple_unsigned, etc.). Fault injection testing via FT-Unshades2 verified full soft error mitigation with minimal code modifications.

Article: Optimal Physical Implementation of Radiation Tolerant High-Speed Digital ICs

electronics Article Optimal Physical Implementation of Radiation Tolerant High-Speed Digital Integrated Circuits in Deep-Submicron Technologies Jeffrey Prinzie, Karel Appels and Szymon Kulis

Abstract: A novel interleaved physical placement strategy for TMR digital circuits was developed in 65 nm CMOS. Compared to conventional 3-bank placement, it reduced total net lengths by up to 65% and dynamic switching power consumption by up to 47% while avoiding MBUs.

Article: Heavy-Ion Induced Single Event Upsets in Advanced 65 nm Rad-Hard FPGAs

electronics Article Heavy-Ion Induced Single Event Upsets in Advanced 65 nm Radiation Hardened FPGAs Chang Cai, Xue Fan, Jie Liu, Dongqing Li, Tianqi Liu, Lingyun Ke, Peixiong Zhao and Ze He

Abstract: A 65 nm SRAM-based FPGA was designed incorporating DICE CRAMs, 8-T DLs, and redundant DFFs. Heavy-ion tests showed CRAM LET threshold of ~18 MeV/(mg/cm2) and saturation cross section of 6.5 × 10^-13 cm2/bit (5 orders of magnitude lower than commercial FPGAs), yielding predicted GEO upset rates of 8.46 × 10^-15 /bit/day.

Article: A Novel Modular Radiation Hardening Approach Applied to a Synchronous Buck Converter

electronics Article A Novel Modular Radiation Hardening Approach Applied to a Synchronous Buck Converter Solomon Banteywalu, Baseem Khan, Valentijn De Smedt and Paul Leroux

Abstract: A four-module redundancy (4MR) architecture for digital DC-DC buck converter controllers on FPGA was proposed. It provides 25% and 30% longer MTTF than TMR and FMR respectively, while using fewer hardware resources than FMR and modified triplex-duplex systems.

Article: A Compact Model to Evaluate the Effects of High Level C++ Code Hardening in Radiation Environments

electronics Article A Compact Model to Evaluate the Effects of High Level C++ Code Hardening in Radiation Environments Leonardo Maria Reyneri, Alejandro Serrano-Cases, Yolanda Morilla, Sergio Cuenca-Asensi and Antonio Martínez-Álvarez

Abstract: A C++ TMR hardening library (TD<DataType>) and a compact parametric reliability estimation model were developed and validated via proton and neutron beam testing on a Xilinx Zynq-7000 SoC running ARM Cortex-A9, enabling rapid optimization of reliability vs. execution time.

Article: Total Ionizing Dose Effects on a Delay-Based Physical Unclonable Function Implemented in FPGAs

electronics Article Total Ionizing Dose Effects on a Delay-Based Physical Unclonable Function Implemented in FPGAs Honorio Martin, Pedro Martin-Holgado, Yolanda Morilla, Luis Entrena and Enrique San-Millan

Abstract: Ring Oscillator PUFs implemented in 90 nm Spartan-3E FPGAs were irradiated with Co-60 gamma rays up to 500 krad(Si). Quality metrics (uniformity, reliability, uniqueness) confirmed that while minor degradation occurs due to delay variations, RO-PUFs remain viable for space cryptographic applications.

Article: Protecting Image Processing Pipelines against Configuration Memory Errors in SRAM-Based FPGAs

electronics Article Protecting Image Processing Pipelines against Configuration Memory Errors in SRAM-Based FPGAs Luis Alberto Aranda, Pedro Reviriego and Juan Antonio Maestro

Abstract: A low-overhead error detection technique using temporary caching registers was developed for line-buffer image processing pipelines in SRAM-FPGAs. Exhaustive fault injection on Xilinx Zynq-7000 demonstrated superior resource efficiency and lower false-positive rates compared to XOR-signature approaches.

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